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features ? sensor keys: ? up to 11 qtouch ? channels ? data acquistion: ? measurement of keys triggered either by a signal applied to the sync pin or at regular intervals timed by th e at42qt1110's internal clock ? keys measured sequentially for better performance, or in parallel groups for faster operation ? raw data for key touches can be read as a report over the spi interface ? discrete outputs: ? configurable ?detect? outp uts indicating individual key touch (7-key mode) ? device setup: ? device configuration can be stored in eeprom ? technology: ? patented spread-spectrum charge-transfer (direct mode) ? key outline sizes: ? 6 mm x 6 mm or larger (panel thicknes s dependent); widely different sizes and shapes possible, includin g solid or ring shapes ? key spacings: ? 7 mm center to center or more (panel thickn ess dependent) ? layers required: ?one ? electrode materials: ? etched copper, silver, carbon, indium tin oxide (ito) ? electrode substrates: ? pcb, fpcb, plastic films, glass ? panel materials: ? plastic, glass, composites, painted surfa ces (low particle dens ity metallic paints possible) ? panel thickness: ? up to 10 mm glass, 5 mm plastic (electrode size dependent) ? key sensitivity: ? individually settable via simple commands over serial interface ? adjacent key suppression ? (aks ? ) ? patented aks technology to enable accurate key detection ? interface: ? full-duplex spi slave mode (750 khz), ?change? pin, discrete detection outputs ? moisture tolerance good ? power: ? 1.8v ~ 5.5v ? package: ? 32-pin 5 x 5 mm mlf rohs compliant ? 32-pin 7 x 7 mm tqfp rohs compliant ? signal processing: ? self-calibration, auto drift compensation, noise filtering, aks technology ? applications: ? consumer and industrial applicatio ns, such as tv, media player, etc qtouch ? 11-key sensor ic at42qt1111-mu AT42QT1111-AU 9571a?at42?02/10
2 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 1. pinout and schematic 1.1 pinout configuration sns0 sns10k/sync sns10/detect6 reset change sns9/detect4 sns8k/detect3 sns3k sns4 sns4k sns5k ss mosi miso sns0k sns1 sns1k vdd vss sns2k sns3 sck vdd sns6k sns6 vss sns7k/detect0 sns7/detect1 sns8/detect2 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 9 10 11 16 15 14 13 12 sns5 sns2 sns9k/detect5 qt1110 qt1111
3 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 1.2 pin descriptions i input only i/o input and output o output only, push-pull od open drain output p ground or power table 1-1. pin listing pin name type comments if unused, connect to... 1 sns0k i/o sense pin leave open 2 sns1 i/o sense pin leave open 3 sns1k i/o sense pin leave open 4 vdd p power ? 5 vss p supply ground ? 6 sns2k i/o sense pin leave open 7 sns2 i/o sense pin leave open 8 sns3 i/o sense pin leave open 9 sns3k i/o sense pin leave open 10 sns4 i/o sense pin leave open 11 sns4k i/o sense pin leave open 12 sns5 i/o sense pin leave open 13 sns5k i/o sense pin leave open 14 ss i enable spi vss via 100 k ? resistor to enable spi vdd via 100 k ? resistor to disable spi 15 mosi i spi data in leave open 16 miso o spi data out leave open 17 sck i spi clock leave open 18 vdd p power ? 19 sns6k i/o sense pin leave open 20 sns6 i/o sense pin leave open 21 vss p supply ground ? 22 sns7k/detect0 i/o sense pin/key status indicator leave open 23 sns7/detect1 i/o sense pin/key status indicator leave open 24 sns8/detect2 i/o sense pin / key status indicator leave open 25 sns8k/detect3 i/o sense pin / key status indicator leave open 26 sns9/detect4 i/o sense pin / key status indicator leave open 27 sns9k/detect5 i/o sense pin / key status indicator leave open 28 change od touch event indicator leave open 29 reset i reset vdd 30 sns10/detect6 i/o sense pin / key status indicator leave open 31 sns10k/sync i/o sense pin / synchronization input vdd or vss via 100 k ? resistor 32 sns0 i/o sense pin leave open
4 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 1.3 schematics figure 1-1. typical circuit: 7 keys with detect outputs and no external trigger vreg vunreg qt1111
5 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU figure 1-2. typical circuit: 11 keys wi th no external trigger vunreg vreg qt1111
6 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU figure 1-3. typical circuit: 10 keys with ex ternal trigger (sync mode) suggested voltage regulator manufacturers: ? torex (xc6215 series) ? seiko (s817 series) ? bcdsemi (ap2121 series) re figure 1-1 , figure 1-2 and figure 1-3 check the following sectio ns for component values: ? section3.1 on page8 : cs capacitors (cs0 ? cs10) ? section3.2 on page8 : sample resistors (rs0 ? rs10) ? section3.5 on page9 : voltage levels ? section3.3 on page8 : led traces vreg vunreg qt1111
7 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 2. overview of the at42qt1111 2.1 introduction the at42qt1111 (qt1111) is a digital burst mode charge-transfer (qt ? ) capacitive sensor driver designed for any touch-key applications. the keys can be constructed in different shapes and sizes. refer to the touch sensors design guide and application note qtan0002, secrets of a successful qtouch? design , for more information on construction and design methods (both downloadable from the atmel ? website). the device includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. only a few external parts are required for operation. the qt1111 modulates its bursts in a spread-spectrum fashion in order to suppress heavily the effects of external noise, and to suppress rf emissions. 2.2 configurations the qt1111 is designed as a versatile device, c apable of various configurations. there are two basic configurations for the qt1111: ? 11-key qtouch. the device can sense up to 11 keys. ? 7-key qtouch with individual outputs for each key. the device can sense up to 7 keys and drive the matching detect outputs to a user-configurable pwm. both configurations allow for a choice of acquisition modes, thus providing a variety of possibilities that will satisfy most applications (see the following se ctions for more information). additionally, the sync line can be used as an external trigger input. note that in 11-key mode the sync line replaces one key, thus allowing only 10 keys. see section 4.7 on page 18 for more information. 2.3 guard channel the device has a guard channel option (available in all key modes), whic h allows one key to be configured as a guard channel to help prevent false detection. see section 4.9 on page 19 for more information. 2.4 self-test functions the qt1111 has two types of self-test functions: ? internal hardware tests ? check for hardware failures in the device?s internal memory. ? functional checks ? confirm that the device is operating within expected parameters. see section 4.10 on page 20 for more information.
8 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 3. wiring and parts 3.1 cs sample capacitors cs0 ? cs10 are the charge sensing sample capacitors. normally they are identical in nominal value. the optimal cs values depend on the thickness of the panel and its dielectric constant. thicker panels require larger values of cs. values can be in the range 2.2 nf (for faster operation) to 33 nf (for best sensitivity); typical values are 4.7 nf to 10 nf. the value of cs should be chosen so that a light touch on a key produces a reduction of ~20 to 30 in the key signal value (see section 6.8 on page 26 ). the chosen cs value should never be so large that the key signals exceed ~1000, as reported by the chip in the debug data. the cs capacitors must be x7r or pps film type, for stab ility. for consistent sensitivity, they should have a 10 percent tolerance. twenty perc ent tolerance may cause small differences in sensitivity from key to key and unit to unit. if a key is not used, the cs capacitor may be omitted. 3.2 rs resistors the series resistors rs0 ? rs10 are inline with th e electrode connections and should be used to limit electrostatic discharge (esd) currents and to suppress radio frequency (rf) interference. values should be approximately 2 k ?? to 20 k ? each; a typical value is 4.7 k ? . although these resistors may be omitted, the device may become susceptib le to external noise or radio frequency interference (rfi). for details of how to select these resistors see the application note qtan0002, secrets of a successful qtouch ? design , downloadable from the touch technology area of at mel?s website, www.atmel.com. 3.3 led traces and ot her switching signals digital switching signals near the sense lines can induce transients into the acquired signals, deteriorating the snr performance of the device. such signals should be routed away from the sensing traces and electrodes, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). led terminals which are multiple xed or switched into a floating state, and which are within, or physically very near, a key (even if on another nearby pcb) should be bypassed to either vss or vdd with at least a 1 nf capacitor. this is to suppress capacitive co upling effects which can induce false signal shifts. the bypass capacitor does not need to be next to the led, in fact it can be quite distant. the bypass capacitor is noncritical and can be of any type. led terminals which are constantly connected to vss or vdd do not need further bypassing. 3.4 pcb cleanliness modern no-clean flux is generally compat ible with capacitive sensing circuits. caution: if a pcb is reworked to correct soldering faults relating to the qt1111, or to any associated traces or components, be sure that you fully understand the nature of the flux used during the rework proces s. leakage currents from hygroscopic ionic residues can stop capacitive sensors from functioning. if you have any doubts, a thorough cleaning after rework may be the only safe option.
9 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 3.5 power supply see section 8.2 on page 38 for the power supply range. if the power supply fluctuates slowly with temperature, the device tracks and compens ates for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. the usual power supply considerations with qt parts apply to the device. the power should be clean and come from a separate regulator if possible. however, this device is designed to minimize the effects of unstable power, and, except in extreme conditions, should not require a separate low dropout (ldo) regulator. see underneath figure 1.3 on page 4 for suggested regulator manufacturers. it is assumed that a larger bypass capacitor (like1 f) is somewhere else in the power circuit; for example, near the regulator. 3.6 mlf package restrictions the central pad on the underside of the mlf chip should be connected to ground. do not run any tracks underneath the body of the chip, only ground. figure 3-1 shows an example of good/bad tracking. figure 3-1. examples of good and bad tracking caution: a regulator ic shared with other logic can result in erratic operation and is not advised. a single ceramic 0.1 f bypass capacitor, with short traces, should be placed very close to the power pins of the ic. failure to do so can result in device oscillation, high current consumption, erratic operation etc. example of good tracking example of bad tracking
10 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 4. detailed operations 4.1 communications 4.1.1 introduction all communication with the device is carried out over the serial peripheral interface (spi). this is a synchronous serial data link that operates in full-duplex mode. the host communicates with the qt controller over the spi using a master-slave relationship, with the qt1111 acting in slave mode. 4.1.2 spi operation the spi uses four logic signals: ? serial clock (sck) ? output from the host. ? master output, slave input (mosi) ? output from the host, input to the qt controller. used by the host to send data to the qt controller. ? master input, slave output (miso) ? input to the host, output from the qt controller. used by the qt device to send data to the host. ? slave select (ss ) ? active low output from the host. at each byte, the master pulls ss low and generates 8 clock pulses on sck. with these 8 clock pulses, a byte of data is transmitted from the ma ster to the slave over mosi, most significant bit (msb) first. simultaneously a byte of data is transmitted from the slave to the master over miso, also most significant bit first. the slave reads the status of mosi at the leading edge of each clock pulse, and the master reads the slave?s data from miso at th e trailing edge. the qt1111 requires that the clock idles ?high?, meaning that the data on mosi and miso pins are set at the falling edges and sampled at the rising edges. that is: clock polarity cpol = 1 clock phase cpha = 1 the qt1111 spi interface can operate at any sck frequency up to 750 khz. in multibyte communications, the master must pause for a minimum delay of 300 s between the completion of one byte exchange and the beginning of the next. note that the number of bytes to be transmitted depends on the initial command sent by the host. this sets the mode on the qt1111 so that the qt1111 knows how to respond to, or how to interpret, the following bytes. if there is a delay of >100 ms between bytes while the qt1111 is waiting for data, or waiting to send data, then the incomplete transmission is discarded and the device resets its spi state machine. it will then in terpret the next byte it receives as a fresh command. when the qt1111 spi interface is receiving a new command, it returns the ?idle? status code (0x55) on miso during the first byte exchange to indicate to the master that it is in the correct state for receiving instructions.
11 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 4.1.3 crc bytes if enabled, a crc checking procedure is implem ented on all communications between the spi master and the qt1111. in this case, each command or report request sent by the master must have a byte appended containing the crc checksum of the data sent. the qt1111 will not respond to commands until the crc byte has been received and verified. sample c code showing the algorithm for calculating the crc of the data can be found in appendix a . when the qt1111 is expecting a crc byte, it returns (on miso) the calculated crc byte which it expects to receive. this is sent simultaneously with the qt1111 receiving the crc byte from the master (that is, during the same byte exchange). this allows both devices to confirm that the data was sent correctly. all data returned by the qt1111 is also be followed by a crc byte, allowing the master to confirm the integrity of the data transmission. 4.1.4 spi commands there are three types of communication between the spi master and the qt1111: ? control commands (see section 5 on page 22 ) ? to send control instructions to the qt1111 ? report requests (see section 6 on page 24 ) ? to reading status information from the qt1111 ? setup commands (see section 7 on page 28 ) ? to set configuration options (?set? instructions) ? to read configuration options (?get? instructions) additionally the ?null? command (0x00) is transmitted by the host device as it is receiving data from the qt1111. 4.1.4.1 control commands a control command is an instruction sent to the qt1111 that controls operations of the device, and for which no response is required. examples of control commands are: ?reset?, ?calibrate?, ?send setups?. with the exception of ?send setups?, control commands normally require a single byte exchange, unless crc checking is enabled, in which case a second byte must be transmitted by the host with the calculated crc of the command byte. figure 4-1. sleep command ? crc disabled host (sends on mosi) device (responds on miso) simultaneous transmission command: 0x05 response: 0x55 ( idle? fresh command) ? ?
12 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU figure 4-2. sleep command ? crc enabled when the ?send setups? command is received, the qt1111 stops measurement of qtouch sensors and waits for 42 bytes of data to be sent. only when all 42 bytes have been received (and the crc byte, if crc is en abled), the qt1111 applies all th e settings to ram and resumes measurement. in this case, if crc is enabled, the crc byte is calculated for all the data sent by the host, including the command byte 0x01. control commands are s pecified in detail in section5 on page22 . 4.1.5 report requests report requests are sent by the host to instruct the qt1111 to return status information. the host sends the appropiate ?report request? command, then transmits null bytes on mosi while the qt1111 returns the report data on miso. figure 4-3. all keys report ? crc disabled host (sends on mosi) command: 0x05 simultaneous transmission command crc: 0x3f response: 0x3f (expected command crc) response: 0x55 ( idle? fresh command) ? ? device (responds on miso) host (sends on mosi) command: 0xc1 device (responds on miso) null: 0x00 key status report byte 0 null: 0x00 key status report byte 1 simultaneous transmission response: 0x55 ( idle? fresh command) ? ?
13 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU for example, figure 4-3 on page 12 shows the exchange that takes place to read the 2-byte ?all keys? report. in this exchange, the host sends: 0xc1 ? 0x00 ? 0x00 and the qt1110 returns (simultaneously): 0x55 ? report byte 0 ? report byte 1 if crc is enabled, this exchange is extended to 5 bytes, as shown in figure 4-4 . figure 4-4. all keys report ? crc enabled 4.1.5.1 set instructions set instructions are 2-byte transmissions by the ho st that are used to send settings to individual locations in the device memory map. at the first byte, the qt1111 return s 0x55 (?idle?) to conf irm that it will interpret the byte as a new command. at the second byte, the qt1111 returns the ?set? command it has just received. for example, to set the ?positive recalibration delay? to 1920 ms, address 5 in the memory map is set to 12 (0x0c). this is done with the ?set? command for address 5 (command code 0x95), as shown in figure 4-5 on page 14 . host (sends on mosi) command: 0xc1 null: 0x00 key status report byte 0 null: 0x00 key status report byte 1 null: 0x00 report crc: 0x?? simultaneous transmission command crc: 0x94 response: 0x94 (expected command crc) response: 0x55 ( idle? fresh command) ? ? device (responds on miso)
14 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU figure 4-5. positive recalibration delay se t instruction ? crc disabled with crc enabled, a crc byte is also required ( figure 4-6 ). this is calculated for the two transmitted bytes (that is, the ?set? command and the data byte). for example, for the sequence shown in figure 4-5 (0x95 ? 0x0c), the crc byte is 0x9f. as is the case with the other command types, when the qt1111 is expecting a crc byte from the host, it calculates that byte in advance and returns the expected value to the host in the same transmission as the host sends the crc byte. the sent data is not applied to the memory location until the crc byte has been received and verified. figure 4-6. positive recalibration delay se t instruction ? crc enabled host (sends on mosi) command: 0x95 ?set? data: 0x0c response: 0x95 (command just received) simultaneous transmission response: 0x55 ( idle? fresh command) ? ? device (responds on miso) host (sends on mosi) command: 0x95 ?set? data: 0x0c response: 0x95 (command just received) simultaneous transmission command crc: 0x9f response: 0x9f (expected crc) response: 0x55 ( idle? fresh command) ? ? device (responds on miso)
15 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 4.1.5.2 get instructions get instructions are instructions that read the data from a location in the qt1111 memory map. figure 4-7. positive recalibration delay ge t instruction ? crc disabled the host sends the appropriate ?get? command, followed by a ?null? byte. the qt1111 returns the contents of the addressed memory location. figure 4-7 on page 15 shows the exchange for a report on the positive recalibration delay (assuming that the data byte is 0x0c). with crc enabled, this exchange takes 4 bytes, with a command crc transmitted by the host and a report crc returned by the qt1111 (see figure 4-8 ). figure 4-8. positive recalibration delay get instruction ? crc enabled host (sends on mosi) command: 0xd5 null: 0x00 ?get? data: 0x0c (positive recalibration delay) simultaneous transmission response: 0x55 ( idle? fresh command) ? ? device (responds on miso) host (sends on mosi) command: 0xd5 null: 0x00 null: 0x00 ?get? crc: 0xa3 simultaneous transmission command crc: 0x68 response: 0x68 (expected command crc) ?get? data: 0x0c (positive recalibration delay) response: 0x55 ( idle? fresh command) ? ? device (responds on miso)
16 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 4.1.6 quick spi mode 4.1.6.1 introduction in quick spi mode, the qt1111 sends a 7-byte key report at each exchange. no host commands are required over spi in this mode; t he host clocks the data bytes out in sequence. 4.1.6.2 quick spi report the 7 report bytes are in the format given in table 4-1 . where: ? byte 0 is a counter that increments from 0 to 254 on successive exchanges to confirm that firmware is operating correctly. ? bytes 1 ? 3 indicate the detect status of channels 0 ? 3, 4 ? 7 and 8 ? 10 respectively (two bits per channel), as follows: ? 00 = channel not in detect ? 01 = channel in detect ? 10 = not allowed ? 11 = invalid signal (channel disabled) ? bytes 4 ? 6 indicate the error status of channels 0 ? 3, 4 ? 7 and 8 ? 10 respectively (two bits per channel), as follows: ?00 = no error ? 01 = not allowed ? 10 = error on channel ? 11 = invalid signal (channel disabled) 4.1.6.3 commands in quick spi mode only two host commands are recognized under quick spi mode. these are shown in table 4-2 . crc checking is not implemented in quick spi mode for host commands or return data. table 4-1. device status report format byte description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 counter counter ? increments from 0 to 255 1 detect status, channels 0 ? 3 channel 3 channel 2 channel 1 channel 0 2 detect status, channels 4 ? 7 channel 7 channel 6 channel 5 channel 4 3 detect status, channels 8 ? 10 reserved channel 10 channel 9 channel 8 4 error status, channels 0 ? 3 channel 3 channel 2 channel 1 channel 0 5 error status, channels 4 ? 7 channel 7 channel 6 channel 5 channel 4 6 error status, channels 8 ? 10 reserved channel 10 channel 9 channel 8 table 4-2. host commands in quick spi mode command code purpose store to eeprom 0x0a allows for ?quick spi mode? to be stored as the default start-up mode enable full spi 0x36 enables full spi mode
17 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 4.1.6.4 quick spi mode timing in quick spi mode, the minimum time betwe en byte exchanges is reduced to 100 s. if a pause in communications of 100 ms is detected during reading of the 7-byte report, the qt1111 resets the exchange, and on the next byte read it returns byte 0 of the report. 4.2 reset the qt1111 can be reset using one of two methods: ? hardware reset: an external reset logic line can be used if desired, fed into the reset pin. however, under most conditions it is acceptable to tie reset to vdd. ? software reset: a software reset can be forced using the ?reset? control command. for both methods, the device will follow the sa me initialization sequen ce. if there any saved settings in the eeprom, these are loaded into ram. ot herwise the default se ttings are applied. note: the spi interface becomes active after the qt1111 has completed its startup sequence, taking approximately 320 ms after power on/reset. 4.3 sleep mode the qt1111 can be put into a very low power sl eep mode (typically < 2 a). during sleep mode, no keys are measured and the detect outputs are all put into high impedience mode to minimize current consumption. th e device remains in sleep mode until a falling edge is detected on either the ss pin or the change pin. when the qt1111 wakes from sleep mode, it continues to operate as it was before it was put into sleep mode. the qt1111 requires approximately 100 s to wake from sleep mode and will not respond correctly to spi communications until the wake-up procedure is complete. the low level on the ss or change pin that is used to wake the device must be maintained for 100 s to ensure correct operation. note: if the device is set to sleep mode for an extended period, the host should initiate a recalibration immediately after waking the qt1111. 4.4 calibration the device can be forced to recalibrate the sensor keys at any time. this can be useful where, for example, a portable device is plugged into mains power, or during product development when settings are being tuned. the qt1111 can also be configured to automatically recalibrate if it remains in detection for too long. this avoids keys becoming ?stuck? after a prolonged period of uninterrupted detection. see section 7.17 on page 37 for details. 4.5 change pin the change pin can be configured using the comms options setup byte (see section 7.5 on page 30 ) to act in one of two modes: ? data mode ?the change pin is asserted (pulled low) when the detection status of a key changes from that last sent to the host; that is when a key-touch or key-release event occurs. ?the change pin is pulled low when a key?s status changes and is only released when the ?send all keys? report is requested (0xc1), or the key status information bytes are read in quick spi mode (see section 7.5 on page 30 ).
18 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU ? touch mode ? the change pin is pulled low when one or mo re keys are in detect. the change pin remains low as long as there is a key in detect, regardless of communications. ?the change pin is released when there are no keys in detect. no host communications are required to release the change pin. 4.6 stand-alone mode the qt1111 can operate in a stand-alone mode without the use of the spi interface. the settings are loaded from eeprom and the device operates in 7-key mode using the detect outputs. 4.7 key modes 4.7.1 11-key mode in 11-key mode, the device can sense up to 11 keys. alternatively, one key can be replaced by the sync line as an external trigger input (see section 4.8.2 on page 19 ). 11-key mode is configured by setting the ?mode ? bit in the device mode setup byte (see section 7.4 on page 29 ). key acquisition can be triggered in one of two ways : using the internal clock to trigger acquisition either at a fixed repetition period or in a continuous ?free run? mode (see section 4.8.1 ), or using the sync pin to provide an external trigger (see section 4.8.2 on page 19 ), 4.7.2 7-key mode in 7-key mode, the detect outputs detect0 to detect6 become active on pins 22?27 and 30. these outputs provide configurable pwm signals that indicate when each of the keys is touched. 7-key mode is configured by clearing the ?mode ? bit in the device mode setup byte (see section 7.4 on page 29 ). each detect output can be individually configured to output a pwm signal while the matching key is in detect or out of detect. this signal can be one of nine levels, ranging from low (pwm = 0 percent) to high (pwm = 100 percent). th is allows for the use of an indicating led. this is achieved by enabling the appropriate bit in the key to led setup byte (see section 7.14 on page 35 ), and setting the desired outputs levels or pwms in setup addresses 9 to 15 (see section 7.12 on page 33 ). 4.8 trigger modes 4.8.1 timed trigger in 11-key mode, the qt1111 can be configured to use the internal clock as a timed trigger. in this case, the qt1111 is configured with a cycle period, such that each acquisition cycle starts a specified length of time after the start of the previous cycle. if the cycle period is set to ?0?, each acquisition cycle starts as soon as the previous one has finished, resulting in the acquisition cycles running back-to-back in a ?free run? mode. the use of a timed trigger, and the cycle period to be used, is set in the device mode setup byte (see section 7.4 on page 29 ).
19 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 4.8.2 synchronized trigger in 11-key mode, if a time trigger is not enabled , the qt1111 operates in ?synchronized? mode. in this mode, sns10k is used as a sync pin to trigger key acquisition, rather than using the device?s internal clock. in this case the maximum number of keys is reduced to 10. the sync pin can use one of two methods to trigger key measurements, selectable via bit 4 of the device mode setup byte (see section 7.4 on page 29 ): low level and rising edge. with the low level method the qt1111 operates in ?free run? mode for as long as the sync pin is read as a logical ?0?. w hen the sync pin goes high, the cu rrent measurement cycle will be finished and no more key measurements will be taken until the sync pin goes low again. the low level trigger should be a minimum of 1 ms so that there is sufficient time for the device to detect the low level. with the rising edge method all enabled keys are measured once when a rising edge is detected on the sync pin. this allows key measurements to be synchronized to an external event or condition. for example, the sync pin can be used by the host to synchronize several devices to each other. this would ensure that only one of th e devices outputs pulses at any given time and signals from one qt1111 do not interfere with the measurements from another. another use for synchronizing to the rising edge is to steady the signals when the device is running off a mains transformer with insufficient mains frequency filtering that is causing a 50hz or 60hz ripple on vdd. if the mains voltage is scaled down with a simple voltage divider and connected to the sync pin, then the key measurement can be triggered by the rising edge detected at a positive going zero -crossing. note that in this ca se, each key signal will be taken at the same point in the cycle, so vdd will be the same at each measurement for a given key and the signals will be steadier. 4.9 guard channel option the device has a guard channel option (available in all key modes), whic h allows one key to be configured as a guard channel to help prevent false detection (see figure 4-9 on page 20 ). guard channel keys should be more sensitive than the other keys (physically bigger or larger cs), subject to burst le ngth limitations (see section 4.11.2 on page 21 ). with guard channel enabled, the designated key is connected to a sensor pad which detects the presence of touch and overrides any output from the other keys using the chip?s aks feature. the guard channel option is enabled by the guard key setup byte (see section 7.5 on page 30 ). with the guard channel not enabled, all the keys work normally. note: if a key is already ?in detect? when the guard channel becomes active, that key will remain in detect and the guard key will not activate until the active key goes out of detect.
20 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU figure 4-9. guard channel example 4.10 self-test functions 4.10.1 internal hardware tests internal hardware tests check for hardware failure in the device?s internal memory areas and data paths. any failure detected in the function or contents of application rom, ram or registers causes the device to reset itself. the application code is scanned with a crc check routine to confirm that the application data is all correct. the ram and registers are checked periodically (every 10 seconds) for dynamic and static failures. 4.10.2 functional checks functional checks confirm that the device is operating within expected parameters; any failure detected in these tests is notified to the system host. the device will continue to operate in the event that such functional failures are detected. the functional tests are: ? check that the channel-measurement si gnals are within the defined range. ? confirm that data stored in the eeprom is valid. these tests are carried out as the particular functions are us ed. for example, the eeprom is checked when the device attempts to load data from eeprom, and the channel signals are checked when a measurement is carried out. note: if a particular channel is unused, the threshold of that channel should be set to 0 to prevent the incorrect reporting of the unused channel as being in an error state. 4.11 signal processing 4.11.1 detection integrator the device features a detection integration mec hanism, which acts to confirm a detection in a robust fashion. a per-key counter is incremented each time the key has exceeded its threshold. when this counter reaches a preset limit the key is finally declared to be touched. for example, if the di limit is set to 10, then a key?s signal must fall by more than the key threshold, and remain below that level for 10 acquisitions, before the key is declared to be touched. similarly, the di is applied to a key that is going out of detect: it must take 10 acquisitions where the signal has not exceeded its detect threshold before it is declared to leave touch. guard channel formed of one key key pad formed of six keys
21 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 4.11.2 burst length limitations the maximum burst length is 2048 pulses. the recommended design is to use a capacitor that gives a signal of <1000 pulses. the number of pulses in the burst can be obtained by reading the key signal (that is, the number of pulses to complete measurement of th e key?s signal) over the spi interface (see section 6.8 on page 26 ). alternatively, a scope can be used to m easure the entire burst, and then the burst length divided by the time for a single pulse. note that the keys are independent of each other. it is therefore possible, for example, to have a signal of 100 on one key and a signal of 1000 on another. 4.11.3 adjacent key suppression technology the device includes atmel?s pat ented adjacent key su ppression (aks) techno logy to allow the use of tightly spaced keys on a keypad wit h no loss of selectability by the user. aks is enabled or disabled for each key indivi dually; only one key out of those enabled for aks may be reported as touched at any one time. the first key touched dominates and stays in detect until it is released, even if another stronger key is reported. once it is released, the next strongest key is reported. if two keys are simulta neously detected, the strongest key is reported, allowing a user to slide a finger across multiple keys with only the dominant key reporting touch. each key can be enable d for aks processing via the aks mask (see section 7.11 on page 33 ). keys outside the group of enabled keys may be in detect simultaneously.
22 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 5. control commands 5.1 introduction the qt1111 control commands are those commands that affect the device operation. the control commands are listed in table 5-1 and are described indivi dually in the following sections. note: commands are implemented immediately upon reception, so a suitable delay is required for the operation to be completed before communications can be re-established. 5.2 send setups (0x01) this command initiates the upload of the full settings table to the qt1111 (see section 7 on page 28 ). when this command is received, the qt1111 stops key measurement and waits until 42 bytes of setup data have been received. key acquisition will restart after all the setup data has been received. if enabled, a crc check byte is transmitted (both ways) after the 42 bytes to confirm that they have been received correctly. if crc checking is not enabled, it is recommended that the host request a dump of setup data from the qt1111, and confirms that the data correctly matches the data sent. the host must wait for at least 300 s for the operation to be completed before communications can be re-established. 5.3 calibrate all (0x03) this command initiates the reca libration of all sensor keys. the host must wait for at least 300 s for the operation to be completed before communications can be re-established. table 5-1. control commands command code note send setups 0x01 configures the device to receive setup data calibrate all 0x03 calibrates all keys reset 0x04 resets the device sleep 0x05 sleep (dead) mode store to eeprom 0x0a stores ram setups to eeprom restore from eeprom 0x0b copies eeprom setups to ra m (automatical ly done at startup) erase eeprom 0x0c erases eeprom setups recover eeprom 0x0d restores last eeprom settings (after erase) calibrate key 'k' 0x1k calibrates one key (key k)
23 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 5.4 reset (0x04) the reset command fo rces the qt1111 to reset. if the setu ps data is present in the eeprom, the setups are loaded into the device. otherwise default settings are applied. the host must wait for at least 160 ms for the operation to be completed before communications can be re-established. 5.5 sleep (0x05) the sleep command puts the device into sleep mode (see section 4.3 on page 17 ). the host must wait for at least 300 s after a low signal is applied to the ss or change pin to wake the device before communications can be re-established. 5.6 store to eeprom (0x0a) stores the current ram contents to the qt1111?s internal eeprom. when the device is reset, it will automatically relo ad these settings. the host must wait for at least 200 ms for the operation to be completed before communications can be re-established. 5.7 restore from eeprom (0x0b) settings stored in eeprom are automatically load ed into ram when the device is reset. if desired, these settings can be re-loade d into ram using the ?rest ore from eeprom? command. the host must wait for at least 150 ms for the operation to be completed before communications can be re-established. 5.8 erase eeprom (0x0c) this command erases the settings stored in eeprom and then resets the qt1111. this causes the qt1111 to revert to its default settings. the host must wait for at least 50 ms for the operation to be completed before communications can be re-established. 5.9 recover eeprom (0x0d) this command ?undeletes? the se tup data that was previously stored in the device?s eeprom and has been erased using the ?erase eepr om? command. note: if valid settings have not previously been stored in the device eeprom, the qt1111 continues to operate under the default settings. the host must wait for at least 50 ms for the operation to be completed before communications can be re-established. 5.10 calibrate key (0x1k) this command recalibrates the key specified by ?k?. for example, to calibrate key 4, the host sends ?0x14?; to calibrate ke y 10, the host sends ?0x1a?. the host must wait for at least 300 s for the operation to be completed before communications can be re-established.
24 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 6. report requests 6.1 introduction the host can request reports from the qt1111, as summarized in table 6-1 . note that spi communications are full-duplex, so the host must transmit on the mosi pin to keep the communications active, while reading data from the qt1111 on the mosi pin. failure to do this within 100 ms will cause the device to assume that th e exchange has been abandoned and reset the spi interface. the host should therefore send one or two ?null? bytes, as appropriate, on the mosi line as it receives the 1- or 2-byte report data from the device. 6.2 first key (0xc0) this command returns 1-byte report in the format shown in table 6-2 . detect: 0 = no key in detect; 1 = there is a key in detect. numkey: indicates the number of keys in detect: 0 = only one key is in detect (specified by ?key_num?) 1 = more than one key in detect. error: 0 = there are no keys in an error state; 1 = at least one key is in error state. key_num: the key number (0 to 10) of the key in detect (if there is only one), or the number of the first key to go into detection when there are more than one. table 6-1. report requests command code note data returned send first key 0xc0 returns the first detected key 1 byte send all keys 0xc1 returns all keys 2-byte bitfield device status 0xc2 returns the device status 1-byte bitfield eeprom crc 0xc3 returns the eeprom crc 1 byte ram crc 0xc4 returns the ram crc 1 byte error keys 0xc5 returns the error keys 2-byte bitfield signal for key ?k?' 0x2k returns the signal for key ?k? 2-byte number reference for key ?k? 0x4k returns the reference for key ?k? 2-byte number status for key ?k? 0x8k returns error conditions/touch indication 1 byte detect output states 0xc6 return s the detect output states 1 byte last command 0xc7 returns the last command sent to qt1111 1 byte setups 0xc8 returns the setup data 42 bytes device id 0xc9 returns the device id 1 byte firmware version 0xca returns the firmware version 1 byte table 6-2. send first key report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 detect numkey error key_num
25 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 6.3 all keys (0xc1) returns a 2-byte bit-field report indicating the detection status of all 11 keys. key_ n : 0 = key n out of detect, 1 = key n in detect (where n is 0 ? 10). 6.4 device status (0xc2) this command returns a 1-byte bit-field report indicating the overall status of the qt1111. bits 7 is always 1; the other bits are as follows: detect: 0 = no key in detect, 1 = at least 1 key in detect. cycle: 0 = cycle time is good, 1 = cycle time over-run. a cycle time over-run occurs when it takes longer to measure and process all the keys than the assigned cycle time. error: 0 = no key in error state, 1 = at least 1 key in error. change: 0 = change pin is asserted, 1 = change pin is floating. eeprom: 0 = eeprom is good, 1 = eeprom has an er ror. if there are no settings stored in eeprom, the eeprom error bit is set an d a zero eeprom crc is returned. reset: set to 1 after power-on or reset, cleared when ?device status? is read. guard: 0 = guard channel is not in det ect, 1 = guard channel is acti ve or in detect. this bit will be zero if the guard channel is not enabled. 6.5 eeprom crc (0xc3) this command returns a 1-byte crc checksum for the setup data in eeprom. 6.6 ram crc (0xc4) this command returns a 1-byte crc checksum for the setup data in ram. table 6-3. send all keys report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 key_10 key_9 key_8 byte 1 key_7 key_6 key_5 key_4 key_3 key_2 key_1 key_0 table 6-4. device status report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 1 detect cycle error change eeprom reset guard
26 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 6.7 error keys (0xc5) this command returns a 2-byte bit-field report indicating the error status of all 11 keys. note that disabled keys do not report errors. key_ n : 0 = key n status good, 1 = key n in error (where n is 0 ? 10). 6.8 signal for key ?k? (0x2k) this command returns a 2-byte report containing the most recent measured signal for key ?k?. the signal is returned as a 16-bit number, msb first. 6.9 reference for key ?k? (0x4k) this command returns a 2-byte report containing the reference signal for key ?k?. the reference is returned as a 16-bit number, msb first. 6.10 status for key ?k? (0x8k) this command returns a 1-byte report containing the status for key ?k?. detect: 0ut of detect, 1 = in detect. lbl: 0 = lower burst limit is good, 1 = lower burst limit has error. mbl: 0 = maximum burst limit is good, 1 = maximum burst limit has error. the maximum burst limit is fixed at 2048 pulses. aks_en: 0 = aks is disabled, 1 = aks is enabled. cal: 0 = normal, 1 = calibrating. key_en: 0 = key is disabled, 1 = key is enabled. table 6-5. send all keys report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 key_10 key_9 key_8 byte 1 key_7 key_6 key_5 key_4 key_3 key_2 key_1 key_0 table 6-6. signal for key ?k? report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 signal msb byte 1 signal lsb table 6-7. reference for key ?k? report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 reference msb byte 1 reference lsb table 6-8. reference for key ?k? report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 detect lbl mbl aks_en cal key_en
27 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 6.11 detect out put states (0xc6) this command returns a byte that indicates whic h pwm signal is applied to each detect pin. det_ n : 0 = ?out of detect? pwm is output, 1 = the ?in detect? pwm is output. note: note: during ?led detect hold time? or ?led fade?, the report indicates the new state of the detect pin. for example, if the dete ct output is in ?led detect hold time? before switching to ?out of detect? pwm, the reported state is ?0?. 6.12 last command (0xc7) this command returns the previous 1-byte command that was received from the host. note that this command does not return itself. 6.13 setups (0xc8) this command returns the 42 bytes of the setups table, starting with address 0, with the most significant bit first. 6.14 device id (0xc9) this command returns 1 byte containing the device id (0x89). 6.15 firmware version (0xca) returns 1 byte containing the firmware version. table 6-9. reference for key ?k? report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 det_6 det_5 det_4 det_3 det_2 det_1 det_0 table 6-10. reference for key ?k? report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 last command table 6-11. device id report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 device id = 0x89 table 6-12. firmware version report format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 major version minor version
28 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 7. setups and status information 7.1 introduction the bytes of the setup table can be written to or read from individually. the setup table and the corresponding ?set? and ?get? commands are listed in table 7-1 . note that there is a discontinuity in the ?set? and ?get? commands; 0xaf and 0xef are not implemented. table 7-1. memory map address function set command get command 0 device mode 0x90 0xd0 1 guard key/comms options 0x91 0xd1 2 detect integrator (di)/drift hold time (dht) 0x92 0xd2 3 positive threshold (p thr)/positive hysterisis (physt) 0x93 0xd3 4 positive drift compen sation (pdrift) 0x94 0xd4 5 positive recalibration delay (prd) 0x95 0xd5 6 lower burst limit (lbl) 0x96 0xd6 7 aks mask: keys 8?10 0x97 0xd7 8 aks mask: keys 0?7 0x98 0xd8 9 detect0 pwm ?detect?/pwm ?no detect? 0x99 0xd9 10 detect1 pwm ?detect?/pwm ?no detect? 0x9a 0xda 11 detect2 pwm ?detect?/pwm ?no detect? 0x9b 0xdb 12 detect3 pwm ?detect?/pwm ?no detect? 0x9c 0xdc 13 detect4 pwm ?detect?/pwm ?no detect? 0x9d 0xdd 14 detect5 pwm ?detect?/pwm ?no detect? 0x9e 0xde 15 detect6 pwm ?detect?/pwm ?no detect? 0x9f 0xdf 16 led detect hold time 0xa0 0xe0 17 led fade/key to led 0xa1 0xe1 18 led latch 0xa2 0xe2 19 key0 negative threshold (nthr)/negative hysterisis (nhyst) 0xa3 0xe3 20 key1 negative threshold (nthr)/negative hysterisis (nhyst) 0xa4 0xe4 21 key2 negative threshold (nthr)/negative hysterisis (nhyst) 0xa5 0xe5 22 key3 negative threshold (nthr /negative hysterisis (nhyst) 0xa6 0xe6 23 key4 negative threshold (nthr /negative hysterisis (nhyst) 0xa7 0xe7 24 key5 negative threshold (nthr)/negative hysterisis (nhyst) 0xa8 0xe8 25 key6 negative threshold (nthr)/negative hysterisis (nhyst) 0xa9 0xe9 26 key7 negative threshold (nthr)/negative hysterisis (nhyst) 0xaa 0xea 27 key8 negative threshold (nthr)/negative hysterisis (nhyst) 0xab 0xeb 28 key9 negative threshold (nthr)/negative hysterisis (nhyst) 0xac 0xec 29 key10 negativethreshold (nthr)/negat ive hysterisis (nhyst) 0xad 0xed 30 reserved ? ? 31 key0 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb0 0xf0
29 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 7.2 setting individual settings to set up an individual setup value, the host sends the command listed under the ?set command? column in table 7-1 , followed by a byte of data. for details of the communication flow, see section4.1 on page10 . 7.3 setting all the setups the host can send all 42 bytes of setup data to the qt1111 as a block using the send setups command. see section 5.2 on page 22 for details. 7.4 address 0: device mode the device mode controls the overall operation of the device: number of keys, acquisition method, timing and trigger mechanism. key_ac: selects the trigger source to start key acquisition; 0 = sync pin, 1 = timed. mode: selects 7-key or 11-key mode; 0 = default 7-key mode, 1 = 11-key mode. signal: selects serial or parallel acquisition of keys signals; 0 = serial, 1 = parallel. sync: selects the trigger type when sync pin is selected as the trigger to start key acquisition. 0 = level acquisition starts when a ?0? is read at the sync pin. if the pin is held low, the qt1111 ope rates in ?free run? mode (that is, it will not sleep in between acquisitions, but start again immediately). 1 = edge acquisition starts when a rising edge is detected at the sync pin. when acquisition and post-processing are completed, the device sleeps until another rising edge is detected at the sync pin. 32 key1 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb1 0xf1 33 key2 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb2 0xf2 34 key3 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb3 0xf3 35 key4 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb4 0xf4 36 key5 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb5 0xf5 37 key6 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb6 0xf6 38 key7 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb7 0xf7 39 key8 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb8 0xf8 40 key9 negative drift compensation (ndrift)/negative recalibration delay (nrd) 0xb9 0xf9 41 key10 negative drift compensation (ndrift)/ negative recalibration delay (nrd) 0xba 0xfa table 7-1. memory map (continued) address function set command get command table 7-2. device mode address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 key_ac mode signal sync repeat_time
30 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU repeat_time: selects the ?repeat? time when ?timed? is selected as the trigger to start key acquisition. the number entered is a multiple of 16 ms. if ?0? is entered, the device will operate in a continuous ?free ru n? mode; that is, the qt1111 will not sl eep after its cycle is completed but will begin the next key acquisition cycle immediately. default key_ac value: 1 (timed) default mode value: 0 (7-key mode) default signal value: 1 (parallel) default sync value: 1 (edge) default repeat_time value: 2 (32 ms cycle) 7.5 address 1: guard key/comms options guard_key: specifies the key (0 to 10) to be used as a guard channel (see section 2.3 on page 7 ) . gd_en: enables the use of a guard key; 0 = disable, 1 = enable. spi_en: enables the quick spi interface; 0 = disable, 1 = enable (see table 7-4 ). see section 4.1.6 on page 16 for details of the quick spi mode report. to exit this mode (and clear the ?spi_en? bit), the command ?0x36? should be sent. to save the settings to eeprom and make qu ick spi mode active on startup, send the ?store to eeprom? command (0x0a). any other data sent is ignored in quick spi mode. chg: the change pin mode (see section 4.5 on page 17 ): 0 = ?data? mode. in this mode the ?change? pin is asserted to indicate unread data. 1 = ?touch? mode. in this mode the ?change? pin is asserted when a key is being touched or is in detect. crc: enables or disables crc; 0 = disable, 1 = ena ble. when this option is enabled, each data exchange must have a crc byte appended. when report or setup data is being returned by the qt1111, a 1-byte checksum is returned. the host should confirm that this checksum is correct and, if not, should request the report again. table 7-3. guard key/comms options address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 guard_key gd_en spi_en chg crc table 7-4. status information bytes byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 counter 1 key 3 status key 2 status key 1 status key 0 status 2 key 7 status key 6 status key 5 status key 4 status 3 reserved key 10 status key 9 status key 8 status 4 key 3 error key 2 error key 1 error key 0 error 5 key 7 error key 6 error key 5 error key 4 error 6 reserved key 10 error key 9 error key 8 error
31 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU where data is being sent by the host, a 1-byte crc should be sent. the qt1111 returns the expected crc byte in the same transaction the crc byte is sent. in this way, the host can immediately determine whether the setup data bytes were received correctly. default guard_key value: 0 (key 0) default gd_en value: 0 (disabled) default chg value: 0 (data mode) default crc value: 0 (disabled) 7.6 address 2: detect integrator limit (dil)/drift hold time (dht) dil: the detection integrator (di) limit. to suppres s false detections caus ed by spurious events like electrical noise, the device incorporates a di counter mechanism. a per-key counter is incremented each time the channel has exceeded its threshold and stayed there for a number of acquisitions in succession, with out going below the threshold level. when this counter reaches a preset limit the channel is finally declared to be touched. if on any acquisition the delta is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. note: a setting of 0 for di is invalid ; the valid range is 1 to 15. dht: the drift hold time. after a key-touch has been removed, the qt1111 pauses in the implementation of its ?drift? compensation for a time. after this time has expired, drift compensation continues as normal. the ?drift ho ld time? is a multiple of 160 ms, providing options from 0 to 2400 ms. default dil value: 3 default dht value: 8 (1280 ms) 7.7 address 3: positive threshold (p thr)/positive hyst eresis (physt) pthr: the positive threshold for the signal. if a ke y signal is significantly higher than the reference signal, this typically indicates that the calibration data is no longer valid. in other words, some factor has changed since the calibr ation was carried out, thus rendering it invalid. generally this is compensated for by the drift, but the greater the difference the longer this will take. in order to speed up this correction, the posi tive threshold is used: if the positive threshold is exceeded, the qt1111 (that is, all keys) is recalibrated. table 7-5. detect integrator/drift hold time address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2dil dht table 7-6. positive threshold (thr)/p ositive hystereis (hyst) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3 pthr physt
32 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU physt: positive hysteresis. this setting provides a greater degree of control over the implementation of the positive threshold recalibration. the positive hysteresis operates as a ?modifier? for the positive threshold. when a key signal is detected as being over the positive threshold, the positive threshol d is reduced by a factor corres ponding to the positive hysteresis so that the key will not go in and out of posit ive detection when the signal is on the borderline between drift-compensation of a positive error or recalibration. the settings for positive hysteresis are: 00 = no change to positive threshold 01 = 12.5 percent reduction in positive-detect threshold 10 = 25% reduction in positive-detect threshold 11 = 37.5% reduction in positive-detect threshold default pthr value: 4 (4 counts above reference) default physt value: 2 (25% positive hysteresis) 7.8 address 4: positive dr ift compensation (pdrift) when changing ambient conditions cause a change in the key signal, the qt1111 will compensate through its drift functions. ?positive drift? refers to the case where the signal for a key is greater than the reference. drift compensation occurs at a rate of 1 count per drift compensation period. pdrift: the drift compensation period, in multiples of 160 ms. the valid range is 0 to 127, where 0 disables positive drift compensation. note: drift compensation timing is paused while drif t hold is activated, and continued when drift hold has timed out. default value: 6 (960 ms) 7.9 address 5: positive r ecalibration delay (prd) if a key signal is determined to be above the positive threshold, the qt1111 will wait for this delay and confirm that the error condition is still present befo re initiating a recalibration. prd: the positive recalibration dela y, in multiples of 160 ms. note: all keys are recalibrated in the case of a positive recalibration. default value: 6 (960 ms) table 7-7. positive drift compensation address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40 pdrift table 7-8. positive recalibration delay address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5prd
33 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 7.10 address 6: lowe r burst limit (lbl) normal qtouch signals are in the range of 100 to 1000 counts for each key. the lower burst limit determines the minimum signal that is consider ed as a valid acquisition. if the count is lower than the lower burst limit, it is considered not to be valid and the key is set to an error state. note: where a key has a signal of less than the lbl, a detection is not reported on that key. default value: 18 7.11 addresses 7?8: aks mask aks_ n (aks mask): 0 = key n aks disabled, 1 = key n aks enabled (where n is 0 ? 10). these bits control which keys have aks enabled (see section 3 on page 8 ). a ?1? means the corresponding key has aks enabled; a ?0? means that the corresponding key has aks disabled. default aks mask: 0x07 and 0xff (all ke ys have aks enabled) 7.12 addresses 9?15: dete ct0 ? detect6 pwm each of the 7 detect pins can be configured to output a pwm signal to indicate whether the key is touched (in detect) or not touched (out of detect). the detect outputs must be enabled by selecting 7-key mode in the ?device mode? setting (see section 7.4 on page 29 ), and the corresponding ?key to led? bits must be set to enable the individual ?detect? outputs for each key (see section 7.14 on page 35 ). in_detect n : pwm to output when key n is ?in detect? (where n is 0 ?7 ). table 7-9. lower burst limit address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6lbl table 7-10. aks mask address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7 aks_10 aks_9 aks_8 8 aks_7 aks_6 aks_5 aks_4 aks_3 aks_2 aks_1 aks_0 table 7-11. detect0 ? detect6 pwm address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 9 in_detect0 out_detect0 10 in_detect1 out_detect1 11 in_detect2 out_detect2 12 in_detect3 out_detect3 13 in_detect4 out_detect4 14 in_detect5 out_detect5 15 in_detect6 out_detect6
34 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU out_detect n : pwm to output when key n is ?out of detect? (where n is 0 ?7 ). this pwm is also output if the detect output is ?disconnected? from the key (that is, ?led_ n ? in address 17 is set to 0), allowing the host to directly control the pwm output. the values for the ?in_detect n ? and ?out_detect n? nibbles are listed in table 7-12 . default in_detect n value: 8 (100% pwm ? on) default out_detect n value: 0 (0% pwm ? off) 7.13 address 16: led detect hold time when a key is touched, if the ?detect? out puts and ?key to led? options are enabled (see section 7.12 and section 7.14 ), the corresponding ?detect? pin will output its ?in-detect? pwm signal. after the key touch is removed, the ?detect? output can be held at the ?in-detect? pwm signal for a time before returning to the ?out of detect? pwm signal. this allows a reasonable length of time for an led to be illuminated. the length of th is time is controlled by the led detect hold time. valid values are in multiples of 16 ms. default value: 0 (0 ms) table 7-12. pwm values value meaning 00% 1 12.5% 225% 3 37.5% 450% 5 62.5% 675% 7 87.5% 8 100% table 7-13. led detect hold time address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 led_detect_hold_time
35 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 7.14 address 17: led fade/key to led fade: enables/disables fading for all leds. this is a global setting; either all leds fade, or none of them. 0 = disable (no fade). 1 = enable fading on and off. led_ n : activates the led output for the corresponding key output detect n (where n is 0 ? 6). 1 = enables the ?detect? output to follow the status of the corresponding key. 0 = disable this function, in which case the ?detect? pin will always output its ?out of detect? pwm (see section 7.12 on page 33 ). default fade value: 0 (disabled) default led_ n value: 1 (enabled) 7.15 address 18: led latch latch_ n : enables/disables latching of the led for the corresponding key output detect n (where n is 0 ? 6). 1 = enables latching. when latching is enabled for a given led, the led toggles its state each time the key is touched. 0 = disables latching. note that bit 7 is reserved and should be set to zero. default latch_ n value: 0x00 (latch disabled) 7.16 addresses 19?29: negativ e threshold (nthr)/negati ve hysteresis (nhyst) table 7-14. led fade/key to led address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 17 fade led_6 led_5 led_4 led_3 led_2 led_1 led_0 table 7-15. led latch address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18 0 latch_6 latch_5 latch_4 latch_3 latch_2 latch_1 latch_0 table 7-16. negative threshold/negative hysteresis address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 19 key_0_nthr key_0_nhsyt 20 key_1_nthr key_1_nhsyt 21 key_2_nthr key_2_nhsyt 22 key_3_nthr key_3_nhsyt 23 key_4_nthr key_4_nhsyt 24 key_5_nthr key_5_nhsyt
36 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU key_ n _nthr: the negative threshold for key n (where n is 0 ? 10). the negative threshold determines how much the signal must fall (compared to the reference) before a key is considered to be ?in detect ?. this level will generally need to be tuned individually for each key. to disable an individual key, set the threshold for that key to 0. key_ n _nhyst: the negative hysteresis applied to key n detection threshold (where n is 0 ? 10). negative hysteresis operates as a ?modifier? for the negative threshold in order to provide a greater degree of control over the detection of a ?touch?. when a key signal is first detected as being under the negative threshold, the threshold is reduced by a factor corresponding to the selected negative hyster esis. this means that the key will not go in and out of detection when the signal is on the borderline between drift-compensation or touch detection. the settings for negative hysteresis are: 00 no change to negative threshold 01 12.5% reduction in negative threshold 10 25% reduction in negative threshold 11 37.5% reduction in negative threshold default key_ n _nthr value: 10 counts default key_ n _nhyst value: 2 (25 percent) 25 key_6_nthr key_6_nhsyt 26 key_7_nthr key_7_nhsyt 27 key_8_nthr key_8_nhsyt 28 key_9_nthr key_9_nhsyt 29 key_10_nthr key_10_nhsyt table 7-16. negative threshold/negative hysteresis (continued) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
37 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 7.17 addresses 31?41: negative drif t compensation (ndrift)/negati ve recalibration delay (nrd) key_ n _ndrift: the negative drift compensation for key n (where n is 0 ? 10). when changing ambient conditions cause a change in the key signal, the qt1111 will compensate through its drift functions. ?negative drift? refers to the case where the signal for a key is lower than the reference. drift compensation occurs at a rate of 1 count per drift compensation period. the entered number is a multiple of 320 ms. note that as a key touch, or an approaching t ouch, naturally causes a negative change in the signal, negative drift should be carried out at a much slower rate than positive drift. otherwise, a slowly approaching finger will no t cause a touch detection, as the falling signal could be compensated through the negative drift mechanism. note: drift compensation timing is paused while drif t hold is activated, and continues when drift hold has timed out. key_ n _nrd: the negative recalibration delay for key n (where n is 0 ? 10). in order to avoid a situation where a key remains ?stuck? in detect due to, for example, changing environmental conditions, the ?negative recalibrat ion delay? sets an upper limit on how long a key can remain ?touched?. when this time is exceeded, the qt1111 (that is, all keys) is recalibrated, taking this key (and any others which are in detect) out of detection. this delay is set in a multiple of 2560 ms. note: a setting of ?0? disables the nrd timeout. default key_ n _ndrift value: 7 (2240 ms) default key_ n _nrd value: 10 (25.6 seconds) table 7-17. negative drift compensation/n egative recalibration delay address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 31 key_0_ndrift key_0_nrd 32 key_1_ndrift key_1_nrd 33 key_2_ndrift key_2_nrd 34 key_3_ndrift key_3_nrd 35 key_4_ndrift key_4_nrd 36 key_5_ndrift key_5_nrd 37 key_6_ndrift key_6_nrd 38 key_7_ndrift key_7_nrd 39 key_8_ndrift key_8_nrd 40 key_9_ndrift key_9_nrd 41 key_10_ndrift key_10_nrd
38 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 8. specifications 8.1 absolute maxi mum specifications 8.2 recommended o perating conditions 8.3 dc specifications 8.4 timing specifications vdd -0.5 to +6v max continuous pin current, any control or drive pin 10 ma voltage forced onto any pin -1.0v to (vdd + 0.5) volts eeprom setups maximum writes 100,000 write cycles caution: stresses beyond those listed under absolute maximum specifications may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other co nditions beyond those indicated in the operational sections of this specification is not imp lied. exposure to absolute maximum specification conditions for extended periods may affect device reliability operating temperature -40c to +c storage temperature -65c to +150c vdd 1.8v to 5.5v supply ripple + noise 20 mv cx transverse load capacit ance per key 2 to 20 pf vdd = 5.0v, cs = 4.7 nf, rs = 1 m ? , ta = recommended range, unless otherwise noted parameter description min typ max units notes iddr average supply current, running ? ? 12 at 5v 8 at 3v ma for typical values see section 8.8 vil low input logic level -0.5v ? 0.3 vdd v vih high input logic level 0.6 vdd vdd vdd + 0.5v v vol low output voltage 0 ? 0.7 v 10 ma sink current voh high output voltage 0.8 vdd ? vdd v 10 ma source current iil input leakage current ? <0.05 1 a rrst internal rst pull-up resistor 30 ? 60 k ? parameter description min typ max units notes t bs burst duration ? 6 ? ms 4.7 nf cs/parallel acquisition fc burst center frequency ? 40 ? khz fm burst modulation, percentage ? 18 ? % t pw pulse width ? 9000 ? s
39 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 8.5 spi bus specifications 8.5.1 general specifications 8.5.2 full spi mode 8.5.3 quick spi mode parameter specification address space 8-bit maximum clock rate 750 khz minimum low clock period 666 ns minimum high clock period 666 ns clock idle high setup on leading (falling) edge clock out on trailing (rising) edge spi enable delay (ss low to sck low) 1 s parameter specification time between bytes 300 s time between communications generally 300 s; longer delays required to implement some commands, as follows: ? send setups: 300 s after all setup bytes are returned ? calibrate all: 300 s ? calibrate key: 300 s ? reset: 320 ms ? sleep: 300 s after a low signal is applied to ss or change to wake the device ? store to eeprom: 200 ms ? restore from eeprom: 150 ms ? erase eeprom: 50 ms ? recover eeprom: 50 ms parameter specification time between bytes 100 s time between communications generally 100 s, except for the following: ? store to eeprom: 200 ms ? switch to full spi: 300 s
40 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU figure 8-1. signals on spi pins during the exchange of a data byte 8.6 external reset 8.7 internal resonator s ample mo s i/mi s o change mo s i pin change mi s o pin s ck ss m s b bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 l s b parameter description operation v rst threshold voltage low (activate) threshold voltage high (release) 0.2vdd 0.9vdd reset minimum length of reset low 600 ns at 5v 1100 ns at 3v parameter operation internal rc oscillator 8 mhz with spread-s pectrum modifier during measurement bursts
41 9571a?at42?01/10 at42qt1111-mu/AT42QT1111-AU 8.8 power consumption 4.7 nf cs capacitors 7-key parallel 7-key serial 11-key parallel 11-key serial 11-key serial, 1 key enabled vdd (v) cycle time actual cycle time idd (a) actual cycle time idd (a) actual cycle time idd (a) actual cycle time idd (a) actual cycle time idd (a) 1.0v 0 (free run) 15.8ms 770 27ms 770 15.8ms 790 36ms 770 4.4ms 745 1 (16 ms nominal) 17.8ms 710 27ms 770 17.9ms 730 36ms 770 16.9ms 380 2 (32 ms nominal) 34.8ms 510 35.4ms 645 34.8ms 495 36ms 770 33.8ms 315 4 (64 ms nominal) 68.4ms 390 69.2ms 465 68.4ms 380 69.6ms 520 67.6ms 285 8 (128 ms nominal) 135ms 330 135ms 370 136ms 315 137ms 390 135ms 270 15 (240 ms nominal) 254ms 305 254ms 320 254ms 295 254ms 325 252ms 260 3.0v 0 (free run) 22.2ms 1450 37.4ms 1435 22.2ms 1530 49.2ms 1480 6.5ms 1260 1 (16 ms nominal) 22.2ms 1450 37.4ms 1435 22.2ms 1530 49.2ms 1480 16.8ms 750 2 (32 ms nominal) 34.6ms 1120 37.4ms 1435 34.6ms 1135 49.2ms 1480 33.4ms 590 4 (64 ms nominal) 67.6ms 785 68.8ms 990 67.6ms 790 69.6ms 1160 66.4ms 505 8 (128 ms nominal) 134ms 625 135ms 990 133ms 605 136ms 800 132ms 470 15 (240 ms nominal) 250ms 545 250ms 990 250ms 520 350ms 630 248ms 450 5.0v 0 (free run) 26.2ms 3680 43.2ms 990 26ms 4080 58.8ms 3180 6.48ms 3425 1 (16 ms nominal) 26.2ms 3680 43.2ms 990 26ms 4080 58.8ms 3180 16.6ms 2135 2 (32 ms nominal) 34.4ms 3125 43.2ms 990 34.2ms 3450 58.8ms 3180 33ms 1705 4 (64 ms nominal) 66.8ms 2320 68ms 990 67.2ms 2430 69.2ms 3115 65.6ms 1530 8 (128 ms nominal) 132ms 1890 133ms 990 132ms 1920 134ms 2275 130ms 1460 15 (240 ms nominal) 246ms 1690 246ms 990 248ms 1640 250 1850 244ms 1425 note: these values are for reference only; values are untested. 10 nf cs capacitors 7-key parallel 7-key serial 11-key parallel 11-key serial 11-key serial, 1 key enabled vdd (v) cycle time actual cycle time idd (a) actual cycle time idd (a) actual cycle time idd (a) actual cycle time idd (a) actual cycle time idd (a) 1.0v 0 (free run) 24.2 ms 775 48.4 ms 805 24.2 ms 790 63.6 ms 785 8.6 ms 785 1 (16 ms nominal) 24.2 ms 775 48.4 ms 805 24.2 ms 790 63.6 ms 785 16.7 ms 460 2 (32 ms nominal) 34.4 ms 595 48.4 ms 805 34 ms 600 63.6 ms 785 33 ms 360 4 (64 ms nominal) 66.8 ms 440 68.4 ms 585 66.4 ms 430 69.6 ms 675 65 ms 305 8 (128 ms nominal) 131 ms 355 133 ms 430 132 ms 345 134 ms 470 130 ms 280 15 (240 ms nominal) 246 ms 320 248 ms 360 246 ms 300 248 ms 370 243 ms 265 3.0v 0 (free run) 24.2 ms 1436 48.4 ms 1470 24.2 ms 1475 63.6 ms 1440 8.6 ms 1320 1 (16 ms nominal) 24.2 ms 1436 48.4 ms 1470 24.2 ms 1475 63.6 ms 1440 16.7 ms 1040 2 (32 ms nominal) 34.4 ms 1390 48.4 ms 1470 34 ms 1430 63.6 ms 1440 33 ms 785 4 (64 ms nominal) 66.8 ms 970 68.4 ms 1335 66.4 ms 1035 69.6 ms 1440 65 ms 635 8 (128 ms nominal) 131 ms 775 133 ms 990 132 ms 680 134 ms 1030 130 ms 570 15 (240 ms nominal) 246 ms 645 248 ms 780 246 ms 565 248 ms 810 243 ms 530 5.0v 0 (free run) 26 ms 4315 56.4 ms 4180 28 ms 4470 73.6 ms 3900 8.6 ms 4140 1 (16 ms nominal) 26 ms 4315 56.4 ms 4180 28 ms 4470 73.6 ms 3900 16.6 ms 3345 2 (32 ms nominal) 34 ms 4315 56.4 ms 4180 34 ms 4470 73.6 ms 3900 32.6 ms 2755 4 (64 ms nominal) 66 ms 3410 67.6 ms 4180 66.4 ms 3230 73.6 ms 3900 64.8 ms 2345 8 (128 ms nominal) 131 ms 2740 132 ms 3205 130 ms 2550 133 ms 3040 129 ms 2180 15 (240 ms nominal) 244 ms 2405 244 ms 2730 242 ms 1520 246 ms 2575 241 ms 2075 note: these values are for reference only; values are untested.
42 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 8.9 mechanical dimensions 8.9.1 at42qt1111-mu ? 32-pin 5 x 5 mm mlf 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 3 2m1-a , 3 2-p a d, 5 x 5 x 1.0 mm body, le a d pitch 0.50 mm, e 3 2m1-a 5/25/06 3 .10 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d1 d e1 e e b a 3 a2 a1 a d2 e2 0.0 8 c l 1 2 3 p p 0 1 2 3 a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a 3 0.20 ref b 0.1 8 0.2 3 0. 3 0 d d1 d2 2.95 3 .10 3 .25 4.90 5.00 5.10 4.70 4.75 4. 8 0 4.70 4.75 4. 8 0 4.90 5.00 5.10 e e1 e2 2.95 3 .10 3 .25 e 0.50 b s c l 0. 3 0 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec s t a nd a rd mo-220, fig. 2 (anvil s ing u l a tion), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k
43 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 8.9.2 AT42QT1111-AU ? 32-pin 7 x 7 mm tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ common dimensions (unit of measure = mm) symbol min nom max note
44 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 8.10 marking 8.10.1 at42qt1111-mu ? 32-pin 5 x 5 mm mlf 5 x 5 mm mlf either of the following markings may be used. 1 32 pin 1 id program week code number 1-52 where: a = 1, b = 2...z = 26 then using the underscore a = 27...z = 52 code revision: 1.0 released 1111 1r0 abbreviation of part number: at42qt 1111 -mu 1 32 pin 1 id abbreviation of part number: at42 qt1111 - mu code revision: 1.0, released datecode/ lot number atmel mu 1r0 qt1111 lot number date code country code
45 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 8.10.2 AT42QT1111-AU ? 32-pin 7 x 7 mm tqfp either of the following markings may be used. 1 32 qt1111 au 1r0 abbreviation of part number: at42 qt1111 - au pin 1 id program week code number 1-52 where: a = 1, b = 2...z = 26 then using the underscore a = 27...z = 52 code revision: 1.0, released 1 32 abbreviation of part number: at42 qt1111 - au pin 1 id code revision: 1.0, released qt1111 au 1r0 atmel date/lot datecode/ lot number
46 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU 8.11 part number 8.12 moisture sensiti vity level (msl) part number description at42qt1111-mu 32-pin 5 x 5 mm mlf rohs compliant (-40c to +85c) AT42QT1111-AU 32-pin 7 x 7 mm tqfp rohs compliant (-40c to +85c) msl rating peak body temperature specifications msl3 260 o c ipc/jedec j-std-020
47 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU appendix a. crc calculation if the use of a cyclic redundancy check (crc) during data transm ission is enabled, the host must generate a valid crc so that this c an be correctly compared to the corresponding crc generated by the qt1111. this appendix gives example c code to show how the crc can be generated by the host. /*======================================================================= unsigned char calc_crc(unsigned char crc, unsigned char data) --------------------------------------------------------------------------- purpose: calculate crc for data packets input : crc, data output : updated crc notes : - =========================================================================*/ unsigned char calc_crc(unsigned char crc, unsigned char data) { unsigned char index; unsigned char fb; index = 8; do { fb = (crc ^ data) & 0x01u; data >>= 1u; crc >>= 1u; if(fb) { crc ^= 0x8c; } } while(--index); return crc; } /* example calling routine */ unsigned char calculate_config_checksum(void) { int i; unsigned char crc_val = 0; unsigned char setup_data[42] = { 0xb2, 0x00, 0x38, 0x12, 0x06, 0x06, 0x12, 0x07, 0xff, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x32, 0xff, 0x00, 0x29, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x7a, 0x7a, 0x7a, 0x7a, 0x7a, 0x7a, 0x7a, 0x7a, 0x7a, 0x7a, 0x7a }; for(i = 0; i < sizeof(setup_data); i++) { crc_val = calc_crc(crc_val, setup_data[i]); } return(crc_val); }
48 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU revision history revision no. history revision a ? february 2010 ? initial release for chip revision 1.0
49 9571a?at42?02/10 at42qt1111-mu/AT42QT1111-AU notes
9571a?at42?02/10 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 01-05 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 touch technology division 1 mitchell point ensign way hamble southampton hampshire so31 4rf united kingdom tel: (44) 23-8056-5600 fax: (44) 23-8045-3939 product contact web site www.atmel.com technical support touch@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with at mel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and conditions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limi tation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibilit y of such damages. atmel makes no representations or warranties with respect to th e accuracy or completeness of the contents of this document and reserves the right to make changes to specif ications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specific ally provided otherwise, atmel products are not suitable for, and shall not be used in, automo tive applications. atmel?s products are not intended, authorized, or warranted for use as componen ts in applications intended to support or sustain life. ? 2010 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, qtouch ? , adjacent key suppression ? and others are registered trademarks, aks ? , qt ? and others are trademarks of atmel corporation or its subsidiaries. other terms and product names may be registered trademarks or trademarks of others.

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